Digital IC Design Engineer (EP-ESE-ME-2025-225-GRAP)
CERN European Organization for Nuclear Research
Geneva
Key information
- Publication date:23 December 2025
- Place of work:Geneva
Job summary
Join CERN as a digital ASIC design engineer, shaping next-gen MAPS. Enjoy a hybrid work environment with competitive benefits.
Tasks
- Design and verify advanced digital readout circuits for detectors.
- Collaborate with specialists to optimize system architectures.
- Manage RTL-to-GDS flow and physical design checks effectively.
Skills
- Master's or PhD in Electronics engineering with relevant experience.
- Proficiency in RTL design using Verilog/SystemVerilog or VHDL.
- Strong scripting skills in Python, TCL, or Shell.
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Job Description
We are looking for a digital ASIC design engineer to work on the next generation of advanced MAPS particle-detector ASICs for the CERN detector complex. You will contribute to the design, implementation, and verification of high-performance digital readout and control circuits that meet demanding targets in speed, density, power efficiency, and radiation tolerance, while collaborating closely with analog and verification specialists.
Your responsibilities:
- Conceive and optimise system-level architectures and data processing strategies.
- Design, synthesise, and implement RTL, including timing closure and place & route of complex designs.
- Contribute to chip signoff through physical design checks (DRC, LVS, ERC) and power integrity analysis.
- Participate in formal verification using UVM methodologies.
- Manage the full RTL-to-GDS flow and physical signoff with professional EDA tools.
- Collaborate and communicate effectively within a multidisciplinary team.
- Learn and share knowledge, solve problems, and achieve results through teamwork.
Your profile:
- Experience in digital IC design with a strong understanding of VLSI principles.
- Experience in the design and implementation of digital or mixed-signal circuits in ASICs or FPGAs.
- Additionally, experience with digital simulation techniques and tools would be an advantage.
Skills:
- Proficiency in RTL design using hardware description languages (Verilog/SystemVerilog, VHDL).
- Proficiency in scripting languages (Python, TCL, Shell) and versioning tools (Git).
- Additionally, experience with functional verification methodologies (UVM/SystemVerilog) and simulation tools would be an advantage.
- Spoken and written English, with a commitment to learn French.
Eligibility criteria:
- You have a professional background in Electronics engineering (or a related field) and have either:
- a Master's degree with 2 to 6 years of post-graduation professional experience;
- or a PhD with no more than 3 years of post-graduation professional experience.
- You have never had a CERN fellow or graduate contract before.
Additional Information
Job closing date: 06.01.2026 at 23:59 CET.
Contract duration: 24 months, with a possible extension up to 36 months maximum.
Job flexibility: Hybrid
Target start date: 01-February-2026
This position involves:
- Work during nights, Sundays and official holidays, when required by the needs of the Organization.
Job reference: EP-ESE-ME-2025-225-GRAP
Field of work: Electrical or Electronics Engineering
Benchmark job: 200050 - Electronics Engineer
Global Benefits
- A monthly stipend between 6287-6911 Swiss Francs per month (tax free) depending on your degree.
- 30 days of paid leave per year plus 2 weeks annual closure.
- Coverage by CERN’s comprehensive health insurance scheme (for yourself, your spouse and children), and membership of the CERN Pension Fund.
- Family, child and infant monthly allowances depending on your individual circumstances.
- A relocation package (installation grant and travel expenses) depending on your individual circumstances.
- Possibility to extend your contract up to 36 months.
- On-the-job and formal training including language classes.
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